Massimo Poncino

Publication List

 

 

Books

1.    A. Macii, L. Benini, M. Poncino,

Memory Design Techniques for Low-Energy Embedded Systems, Kluwer Academic Publishers, 2002.

 

 

 

Book Chapters

1.    “Micro-Architectural Power Estimation and Optimization,”

E. Macii, R. Mehra, M. Poncino,

in Handbook of EDA for IC Design,

G. Martin, L. Lavagno, and L. Scheffer Editors,

CRC Press, Boca Raton, Florida, 2005.

2.    “System-Level Dynamic Power Management,”

N. Chang, E. Macii, M. Poncino, V. Tiwari,

in Handbook of EDA for IC Design,

CRC Press, Boca Raton, Florida, 2005.

3.    E. Macii, M. Poncino,

“Power Macro-Models for High-Level Power Estimation”,

in Low Power Electronics Design,

C. Piguet Editor, CRC Press, Boca Raton, Florida, 2004.

4.    K. Patel, E. Macii, M. Poncino,

“Energy-Efficient Shared-Memory Architectures for Multi-Processor Systems-on-Chip,”

in Ultra Low-Power Electronics and Design,

Kluwer Academic Publishers, Boston, 2003.

5.    L. Benini, M. Poncino,

Ambient Intelligence: A Computational Perspective,

in ’Ambient Intelligence: Impact on Embedded-system Design,

Kluwer Academic Publishers, Boston, 2003.

 

 

Papers on Refereed Journals

 

1.    A. Lioy, M. Poncino,

“A Study of the Resetability of Synchronous Sequential Circuits,”

Microprocessing and Microprogramming,

Vol. 38, pp. 395–402, November 1993.

2.    D. Alovisio, S. Cianchini, E. Macii and M. Poncino,

“A Sequential Circuit Simulator Based on Hybrid Cellular Automata”,

Systems Analysis, Modelling and Simulation,

Vol. 16, pp. 245–253, 1994.

3.    D. Alovisio, S. Cianchini, E. Macii, M. Poncino,

“Modeling Sequential Circuits with Cellular Automata”,

International Journal of Systems Science,

Vol. 26, No. 7, pp. 1415–1428, July 1995.

4.    E. Macii, M. Poncino,

The Impact of Cell Library Characteristics on Area, Speed, and Power Consumption of CMOS Circuits,”

International Journal on Electronics,

Vol. 78, No. 2, pp. 395–407, 1995.

5.    E. Macii, M. Poncino,

“Symbolic Representation and Manipulation of Large Neural Networks”,

ISCA International Journal on Computers and their Appplications,

Vol. 11, No. 2, pp. 104–111, August 1995.

6.    E. Macii, M. Poncino,

"Using Connectivity and Spectral Methods to Characterize the Structure of Sequential Logic Circuits,"

Microprocessing and Microprogramming,

Vol. 41(1995), pp. 487–500.

7.    E. Macii and M. Poncino,

“Using Symbolic Rademacher-Walsh Spectral Transforms to Evaluate the Agreement

Between Boolean Functions”,

IEE Proceedings – Computers and Digital Techniques,

Vol. 143, No. 1, pp. 64–68, January 1996.

8.    E. Macii, M. Poncino,

“Estimating Power Consumption of CMOS Circuits Modeled as Symbolic Neural Networks”,

IEE Proceedings – Computers and Digital Techniques,

Vol. 143, No. 5, pp. 331–336, September 1996.

9.    H. Cho, G. D. Hachtel, E. Macii, M. Poncino, and F. Somenzi,

"Automatic State Space Decomposition for Approximate FSM Traversal Based on

Circuit Structural Analysis,"

IEEE Transactions on CAD,

Vol. 15, No. 12, pp. 1451–1464, December 1996.

10.  E. Macii, M. Poncino,

“ An Exact Algorithm for Computing the Entropy of a Logic Circuit,”

ISCA: International Journal on Computers and their Applications,

Vol. 4, No. 2, pp. 49-55, 1997.

11.  E. Macii, M. Poncino,

“An Application of Hopfield Neural Networks to Symbolic Power Analysis of VLSI Digital Circuits,”

International Journal of Engineering Science,

Vol. 35, No. 8, pp. 783-792, 1997.

12.  E. Macii, M. Poncino,

“Predicting the Complexity of Large Combinational Circuits Through Symbolic Spectral Analysis

of their Functional Specifications”,

IEE Proceedings – Computers and Digital Techniques,

Vol. 144, No. 5, pp. 343-347, 1997.

13.  E. Macii, M. Poncino,

“Cellular Automata Models for Reliability Analysis of Systems on Silicon,”

IEEE Transactions on Reliability,

Vol. 46, No. 2, June 1997, pp. 173–183.

14.  F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto,

“Testing Core-Based Digital Systems: A Symbolic Methodology”,

IEEE Design & Test, Vol. 14, No. 4, pp. 69–77, October/December 1997.

15.  A. H. Evans, E. Macii, M. Poncino,

“Re-Synthesis for Testability of Redundant Combinational Circuits”,

Microcomputer Applications,

Vol. 17, No. 1, pp. 8-11, 1998.

16.  E. Macii, M. Poncino,

“Automatic Synthesis of Easily Scalable Architecture for Bus Arbiters with

Dynamic Priority Assignment Strategies,”

Computers and Electrical Engineering: An Internation Journal, Vol. 24 (1998), pp. 223–228.

17.  L. Benini, G. De Micheli, E. Macii, M. Poncino,

“Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs”

IEEE Transactions on CAD, Vol. 17, No. 3, pp. 220–232, March 1998.

18.  L. Benini, G. De Micheli, E. Macii, M. Poncino, S. Quer,

“Power Optimization of Core-Based Systems by Address Bus Encoding,”

IEEE Transactions on VLSI Systems, Vol. 6, No. 4, pp. 554-562, Dicembre 1998.

19.  L. Benini, G. De Micheli, A. Macii, E. Macii, M. Poncino,

“A Methodology for the Automatic Selection of Instruction Op-Codes of Low-Power Core Processors,”

IEE Proceedings – Computer & Digital Techniques, Vol. 146, No. 4, July 1999, pp. 173–178.

20.  L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, M. Poncino,

“Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting,”

IEEE Transactions on Computers, Vol.  48, No. 8 , pp. 769–779, August 1999.

21.  M. Baldi, E. Macii, M. Poncino,

“Probabilistic Analysis and Verification of Communication Protocols Based on

Symbolic FSM Manipulation”

IEE Proceedings – Computer & Digital Techniques, Vol. 146, No. 5, September 1999, pp. 221–226.

22.  L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi,

“Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Synchrounous Controllers,”

ACM Transactions on Design Automation of Electronic Systems, Vol. 4, No. 4, October 1999, pp. 351–375.

23.  L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi,

“A Multi-Level Scheme for Fast Power Simulation of Realistic Input Streams,”

IEEE Transactions on CAD, Vol. 19, No. 3, April 2000, pp. 459–472.

24.  L. Benini, A. Macii, E. Macii, M. Poncino,

“Increasing Energy Efficiency of Embedded Systems by Application-Specific

Memory Hierarchy Generation,”

IEEE Design and Test, Vol. 17, No. 2, April/June 2000, pp. 74–85.

25.  L. Benini, G. De Micheli, A. Macii, E. Macii, M. Poncino, R. Scarsi,

“Glitch Power Minization by Selective Gate Freezing”,

IEEE Transactions on VLSI Systems, Vol. 8, No. 3, June 2000, pp. 287–298.

26.  F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto,

"Symbolic Optimization of FSM Networks Based on Redundancy Identification and Removal”,

IEEE Transactions on CAD, Vol. 19, No. 7, July 2000, pp. 760–772.

27.  L. Benini, A. Macii, E. Macii, M. Poncino, R. Scarsi,

Architectures and Synthesis Algorithms for Power-Efficient Bus Interfaces”,

IEEE Transactions on CAD, Vol. 19, No. 9, September 2000, pp. 969–980.

28.  A. Macii, E. Macii, M. Poncino, R. Scarsi,

“Stream Synthesis for Efficient Power Simulation Based on Spectral Transforms,”

IEEE Transactions on VLSI Systems, Vol. 9, No. 1, June 2001, pp  417–426.

29.  L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, M. Poncino,

“Synthesis of Power-Managed Sequential Components Based on Computational kernel Extraction,”

IEEE Transactions on CAD, Vol. 9, No. 9, September 2001, pp .1118–1131.

30.  L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, R. Scarsi,

“Discrete-Time Battery Models for System-Level Low-Power Design”,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems,

Vol. 9, No. 5, pp. 630-640, October 2001.

31.  A. Bogliolo, R. Corgnati, E. Macii, M. Poncino,

“Parameterized RTL Power Models for Soft Macros”,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems,

Vol. 9, No. 6, pp. 880-887, December 2001.

32.  A. Macii, E. Macii, M. Poncino,

“Current-Controlled Battery Management Policies for Lifetime Extension of Portable Systems”,

ST Journal of System Research,

Vol. 3, No. 1, pp. 92-99, April 2002.

33.  L. Benini, L. Macchiarulo, A. Macii, E. Macii, M. Poncino,

“Layout-Driven Memory Synthesis for Embedded Systems-on-Chip,”

IEEE Transactions on VLSI Systems,

Vol. 10, No. 2, pp. 96-105, April 2002.

34.  M. Baldi, A. Macii, E. Macii, M. Poncino,

“VHDL Simulation: A Flexible Approach to Protocol Verification and Performance Analysis”,

Systems Analysis, Modelling and Simulation,

Vol. 42, No. 6, pp. 925-938, June 2002.

35.  L. Benini, A. Macii, E. Macii, M. Poncino,

“Minimizing Memory Access Energy in Embedded Systems by Selective Instruction Compression”,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems,

Vol. 10, No. 5, pp. 521-531, October 2002.

36.  L. Benini, A. Macii, M. Poncino,

“Energy-Aware Design of Embedded Memories: A Survey of Technologies, Architectures and Optimization Techniques”,

ACM Transactions on Embedded Computing Systems,

Vol. 2, No. 1, pp. 5–32, February 2003.

37.  L. Benini, D. Bertozzi, D. Bruni, N. Drago, F. Fummi, M. Poncino,

“SystemC Co-Simulation and Emulation of Multi-Processor Systems-on-Chip,”

IEEE Computer,

Vol. 36, No. 4, pp. 53–59, April 2003

38.  L. Benini, D. Bruni, A. Macii, E. Macii, M. Poncino,

“Extending Lifetime of Multi-Battery Mobile Systems by Discharge Current Steering”,

IEEE Transactions on Computers,

Vol. 52, No. 8, pp.985-995, August 2003.

39.  L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, R. Scarsi,

“Scheduling Battery Usage in Mobile Systems”,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems,

Vol. 11, No. 6, pp.1136-1143, December 2003.

40.  S. Salerno, E. Macii, M. Poncino,

“Energy-Efficient Bus Encoding for LCD Digital Display Interfaces,”

IEEE Transactions on Consumer Electronics,

Vol. 51, No. 2,  pp. 624--634, May 2005.

41.    M. Bruno, A. Macii, M. Poncino,

“RTL Power Estimation in an HDL-Based Design Flow,”

IEE Proceedings – Computer & Digital Techniques,

Vol. 152, No. 3, pp. 723-730, May 2005.

42.    M. Loghi, L. Benini, M. Poncino,

``Cache Coherence Tradeoffs in Shared Memory MPSoCs,''

ACM Transactions on Embedded Computing Systems,

Vol. 5, No. 2, May 2006, pp. 383--407.

43.    K. Patel, E. Macii, M. Poncino, L. Benini

``Energy-Efficient Value Based Selective Refresh for Embedded DRAMS”'

Journal of Low Power Electronics, Vol. 2, No. 1, pp.70--79,  April 2006.

44.    M. Poncino, E. Macii,

``Low-Energy RGB Color Approximation for Digital LCD Interfaces''

IEEE Transactions on Consumer Electronics,

Vol. 153, No. 4, pp. 1004-1012, August 2006.

45.    K. Patel, L. Benini, E. Macii, M. Poncino,

``Reducing Conflict Misses by Application-Specific Re-Configurable Indexing'',

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,

Vol. 25, No. 12,  pp. 2626-2637,  December 2006.

46.    F. Poletti, A. Poggiali, D. Bertozzi, L. Benini, P. Marchal, M. Loghi, M. Poncino,
``Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support”,
IEEE Transactions on Computers,
Vol. 56, No. 5, pp.~606-621. May 2007.

47.    F. Fummi, M. Loghi, G. Perbellini, M. Poncino
”SystemC co-simulation for core-based embedded systems”
Design Automation for Embedded Systems, Vol.11 pp.141-166, Sept. 2007

48.    L. Benini, M. Loghi, M. Poncino,

``Power Macromodeling of MPSoC Message Passing Primitives,''

ACM Transactions on Embedded Computing Systems,

Vol. 6, No. 4, pp. 31/1-31/22, October 2007.

49.    A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, M. Poncino,

``Implementation of a Thermal Management Unit for Canceling Temperature-Dependent Clock Skew Variations'',

Integration,  Vol. 41,  No. 1, pp.  2-8. January 2008.                                                            

50.    A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, M. Poncino,

``Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers”,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 6, June 2008, pp. 639-649.

51.    A. Calimera, K. Duraisami, A. Sathanur, P. Sithambaram, R. I. Bahar, A. Macii, E. Macii, and M. Poncino
”Thermal-Aware Design Techniques for Nanometer CMOS Circuits”
Journal of Low Power Electronics,  Vol. 4, No. 3, pp. 374–384, December 2008.

52.    A. Sathanur,  L. Benini, A. Macii,  E. Macii, M. Poncino,
“Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating”,
Journal of Low Power Electronics,  Vol. 5, No. 1, April 2009, pp. 113-121.

53.    F.Fummi, M.Loghi, M.Poncino, G.Pravadelli
”Co-Simulation Methodology for HW/SW Validation and Performance Estimation”,
ACM Transactions on Design Automation of Electronic Systems, No. 14, Vol 2. pp. 23-1, 23-32, April 2009.

54.    M. Loghi, P. Azzoni, M. Poncino
“Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching”,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol 17, No. 5, pp. 728-732, May 2009.

55.    A. Calimera, L. Benini, A. Macii, E. Macii, M. Poncino
“Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits”,
IEEE Transactions on Circuit and Systems I, Vol, 56, No. 9, pp. 1979-1993, September 2009.

56.    L. Benini, A. Bocca, A. Bonanno, A. Macii, E. Macii, J.L. Nagel, C. Piguet, M. Poncino
A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits”

         Journal of Low Power Electronics, Volume 6, Number 1, pp. 44-55, April 2010.

57.    M. Loghi, O.Golubeva, E. Macii, M. Poncino,
”Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Sub-Banking”,
IEEE Transactions on Computers, Vol. 59, No. 7, July 2010, pp. 891—904.

58.    A. Calimera, R. I. Bahar, E. Macii, M. Poncino,
 ” Dual-Vt assignment policies in ITD-aware synthesis”,
Microelectronics Journal, 2010, Vol. 41, No. 9, September 2010, pp. 547—553.

59.    A. Chakraborty, K. Duraisami, P. Sithambaram, A. Macii, E. Macii, and M. Poncino,
”Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs”,
IEEE Transactions on Circuit and Systems I, Vol, 57, No. 10, October 2010, pp. 2741-2752.

60.    A. Calimera, R. Iris Bahar, E. Macii, M. Poncino,
“Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol 18, No. 11,  November 2010, pp. 1608—1620.

61.    A. Calimera, E. Macii, M. Poncino,
 “NBTI-Aware Clustered Power Gating”
ACM Transactions on Design Automation of Electronic Systems, to appear, Vol  16, No. 1, pp. 3:1—3:25, November 2010.

62.    A.  Sathanur, L. Benini, A. Macii, E. Macii, M. Poncino,
”Fast Computation of Discharge Current Upper Bounds for Clustered Power-Gating”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol .19 , No. 1, January 2011, pp.-146-151.

63.    A.  Sathanur, L. Benini,, A. Macii, E. Macii, M. Poncino,
”Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits”,
 
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol .19, No. 3, March 2011,  pp. 469-482.

64.    A. Calimera, E. Macii, M. Poncino,
 “Design Techniques for NBTI-Tolerant Power-Gating Architectures”,
IEEE Transactions on
on Circuits and Systems II, 2011, to appear.

65.    L. Max de Lima Silva, A. Calimera, A. Macii, E. Macii, M. Poncino,
 “Power Efficient Variability Compensation through Clustered Tunable Power-Gating”,
IEEE Journal of Emerging Technologies in Circuits and Systems, to appear, 2011.

66.    A. Calimera, A. Macii, E. Macii, M. Poncino,
Design Techniques and Architectures for Low-Leakage SRAMs”,
IEEE Transactions on Circuit and Systems I, to appear, 2012.




 

 

 

 

 


 

Papers in Conference Proceedings

 

1.    A. Lioy, M. Poncino,

“A Hierarchical Multi-Level Test Generation System,”

GLS-VLSI’91: 1st Great Lake State Symposium,

Kalamazoo, Michigan, February–March 1991, pp. 54–59.

2.    S. Gai, A. Lioy, M. Poncino,

“Generazione di Test per Circuiti Sequenziali Sincroni”,

Congresso Annuala AICA’92:,

Torino, October 1992, pp. 757–767

3.    A. Lioy, M. Poncino,

“On the Resetability of Synchronous Sequential Circuits,”

ISCAS’93: IEEE Int. Symp. on Circuits and Systems,

Chicago, Illinois, May 1993, pp. 1507–1510

4.    H. Farhat, A. Lioy, M. Poncino,

“Exact Computation of Detectability Profile,”

CICC’93: IEEE Custom Integrated Circuits Conference,

S. Diego, CA, May 1993, pp. 26.7.1–26.7.4

5.    E. Macii, M. Poncino,

“Experiments on Technology Mapping Using Different Cell Libraries,”

IEEE Fifth NASA Symposium on VLSI Design,

Albuquerque, New Mexico, November 1993, pp. 9.3.1–9.3.9

6.    R.I. Bahar, G.D. Hachtel, E. Macii, A. Pardo, M. Poncino, and F. Somenzi,

“An ADD-Based Algorithm for Shortest Path Back-Tracing of Large Graphs”.

GLS-VLSI’94: 4th IEEE Great Lake Symposium on VLSI,

South Bend, Indiana, March 1994, pp. 248–251.

7.    H. Cho, G.D. Hachtel, E. Macii, M. Poncino, and F. Somenzi,

“A State Space Decomposition Algorithm for Approximate FSM Traversal”,

EDAC’94: IEEE European Conference on Design Automation,

Paris, February–March 1994, pp. 137–141.

8.    G.D. Hachtel, M. Hermida, A. Pardo, M. Poncino, and F. Somenzi,

“Re-encoding Sequential Circuits to Reduce Power Dissipation,”

IEEE International Workshop on Low Power Design,

Napa, CA, March 1994, pp. 69–74.

9.    E. Macii, M. Poncino,

“FPGA Synthesis Using Look-Up Table and Multiplexor Based Architectures”

MELECON’94: IEEE Mediterranean Electrotechnical Conference,

Antalya, Turkey, April 1994, pp. 302–305.

10.  E. Macii, M. Poncino,

“The Influence of Cell Library Characteristics on Power Consumption of CMOS Circuits”

MELECON’94: IEEE Mediterranean Electrotechnical Conference,

Antalya, Turkey, April 1994, pp. 537–540.

11.  A.H. Evans, E. Macii and M. Poncino,

“Synthesis of Fully Testable Combinational Logic,”

MWSCAS’94: IEEE Midwest Symposium on Circuits and Systems,

Lafayette, Lousiana, August 1994, pp. 230–233.

12.  E. Macii and M. Poncino,

“Connectivity and Spectral Analysis of Finite State Machines,”

MWSCAS’94: IEEE Midwest Symposium on Circuits and Systems,

Lafayette, Lousiana, August 1994, pp. 377–380.

13.  M. Poncino,

"Applications of Boolean Unification to Logic Synthesis,"

IEEE Canadian Conference on Electronic and Computer Engineering,

Halifax, Canada, September 1994, pp. 553–556.

14.  E. Macii and M. Poncino,

"Look-Up Table FPGA Realization of m-out-of-n Bit Voters,"

IEEE Canadian Conference on Electronic and Computer Engineering,

Halifax, Canada, September 1994, pp. 190–193.

15.  E. Macii and M. Poncino,

“The Impact of Gate Delay Models on Power Estimation for CMOS Circuits”

ASICON’94: 1994 IEEE International Conference on ASIC,

Beijing, China, October 1994, pp. 41–44.

16.  D. Alovisio, S. Cianchini, E. Macii and M. Poncino,

“Describing Input Behavior of Sequential Circuits Modeled as Cellular Automata,”

ASICON’94: 1994 IEEE International Conference on ASIC,

Beijing, China, October 1994, pp. 79–82.

17.  E. Macii and M. Poncino,

“STG Characteristics of the ISCAS’89 Benchmarks”,

ASICON’94: 1994 IEEE International Conference on ASIC,

Beijing, China, October 1994, pp. 177-180.

18.  A. H. Evans, E. Macii, M. Poncino,

“Adding Control Signals to Enhance Circuit Testability”,

ASICON’94: IEEE International Conference on ASIC,

Beijing, China, October 1994, pp. 495–498.

19.  H. Cho, G.D. Hachtel, E. Macii, M. Poncino, and F. Somenzi,

“A Structural Approach to State Space Decomposition for Approximate Reachability Analysis,”

ICCD’94: IEEE International Conference on Computer Design,

Cambridge, Massachusets, October 1994, pp. 236–239.

20.  G.D. Hachtel, M. Hermida, A. Pardo, M. Poncino, and F. Somenzi,

“Re-encoding Sequential Circuits to Reduce Power Dissipation,”

ICCAD’94: ACM/IEEE International Conference on CAD,

San Jose, CA, November 1994, pp. 70–73.

21.  E. Macii and M. Poncino,

“Using Symbolic Rademacher-Walsh Spectral Transforms to Evaluate the Correlation between Boolean Functions”,

GLS-VLSI’95: 5th IEEE Great Lake Symposium on VLSI,

Buffalo, New York, March 1995, pp. 112–116.

22.  E. Macii and M. Poncino,

“Estimating Worst Case Power Consumption of CMOS Circuits Modeled as Symbolic Neural Networks”,

GLS-VLSI’95: 5th IEEE Great Lake Symposium on VLSI,

Buffalo, New York, March 1995, pp. 60–65.

23.  E. Macii, M. Poncino,

“Symbolic Representation and Manipulation of Large Neural Networks”,

ISCA International Conference on Computers and Medicine,

Indianapolis, Indiana, March 1995, pp. 112–116.

24.  A. Lioy, M. Poncino

“Exact Functional Redundancy Identification”,

IEEE Pacific Rim Conference on Communications, Computer and Signal Processing,

Victoria, Canada, May 1995, pp. 465–468.

25.  A. Lioy, F. Maino, G. Odasso, M. Poncino

“Testing Hyperactive Faults in Asynchronous Circuits”,

IEEE Pacific Rim Conference on Communications, Computer and Signal Processing,

Victoria, Canada, May 1995, pp. 473–476.

26.  H. Cho, G.D. Hachtel, E. Macii, M. Poncino, K. Ravi, and F. Somenzi,

“Approximate Finite State Machine Traversal: Extensions and New Results”

IWLS’95: ACM/IEEE International Workshop on Logic Synthesis,

Tahoe City, CA, May 1995, Paper 3–1.

27.  S. Manne, A. Pardo, R.I. Bahar, E. Macii, M. Poncino, G.D. Hachtel, and F. Somenzi,

“On Computing the Maximum Power Cycles of a Sequential Circuit”,

DAC-32: 32nd Design Automation Conference,

San Diego, CA, June 1995, pp. 23–28.

28.  E. Macii, M. Poncino,

“Predicting the Complexity of Large Combinational Circuits

by Symbolic Spectral Analysis of Boolean Functions,”

Euro-DAC’95: European Design Automation Conference,

Brighton, Inghilterra, September 1995, pp. 294–299.

29.  E. Macii, M. Poncino,

“The Design of Easily Scalable Bus Arbiters with Different Dynamic Priority Assignment Schemes,”

29th Annual Asilomar Conference on Signals, Systems and Computers,

Monterey, CA, November 1995, pp. 211–213.

30.  M. Baldi, E. Macii, M. Poncino,

“Hardware Simulation: A Flexible Approach to Verification and Performance Evaluation of Communication Protocols,”

29th Annual Asilomar Conference on Signals, Systems and Computers,

Monterey, CA, November 1995, pp. 945–948 .

31.  F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto,

“Test Generation for Networks of Interacting FSMs Using Symbolic Techniques,”

GLS-VLSI’96: 6th IEEE Great Lake Symposium on VLSI,

Ames, Iowa, March 1996, pp. 208–213.

32.  E. Macii, M. Poncino

“Exact Computation of the Entropy of a Logic Circuit,”

GLS-VLSI’96: 6th IEEE Great Lake Symposium on VLSI,

Ames, IA, March 1996, pp. 137–142.

33.  F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto,

“Symbolic Optimization of FSM Networks based on Sequential ATPG Techniques”,

DAC’96: 33th ACM/IEEE Design Automation Conference,

Las Vegas, NV, June 1996, pp. 467–470.

34.  F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto,

“Simplifying Sequential Gate-Level Test Generation Through Exploitation of High-Level Information,”

ETW’96: IEEE European Test Workshop,

Montpellier, France, June 1996, pp. 154–158.

35.  M. Poncino,

“Implicit Evaluation of Encoding Rotations for Large FSMs,”

MWSCAS’96: IEEE Midwest Symposium on Circuits and Systems,

Ames, Iowa, August 1996, pp. 1321–1324.

36.  M. Baldi, E. Macii, M. Poncino,

“Property Verification and Performance Evaluation of Communication Protocols Based on Probabilistc Analysis,”

MWSCAS’96: IEEE Midwest Symposium on Circuits and Systems,

Ames, Iowa, August 1996, pp. 1143–1146.

37.  F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto,

“BDD-Based Testability Estimation of VHDL Designs”,

IEEE EuroVHDL Conference,

Ginevra, Switzerland , September 1996, pp. 444–449.

38.  G. Cabodi, P. Camurati, L. Lavagno, E. Macii, M. Poncino, S. Quer, E. Sentovich,

“Enhancing FSM Traversal by Temporary Re-Encoding,”

ICCD’96: International Conference on Computer Design,

Austin, Texas, October 1996, pp. 6–11.

39.  M. Baldi, E.  Macii, and M. Poncino,

“Efficient Analysis of Communication Protocols using VHDL Modeling and Simulation,”

ASICON’96: IEEE International Conference on ASIC,

Shangai, China, October 1996, pp 428–431.

40.  E.  Macii, and M. Poncino,

“Power Consumption of Static and Dynamic CMOS Circuits: A Comparative Study,”

ASICON’96: IEEE International Conference on ASIC,

Shangai, China, October 1996, pp 425–427.

41.  A. Lioy, E. Macii, M. Poncino, M. Rossello,

“Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering”,

GLS-VLSI’97: IEEE 7th Great Lakes Symposium on VLSI,

Urbana-Champaign, Illinois, March 1997, pp. 70–75.

42.  L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi,

“Symbolic Low-Power Re-Synthesis of Large Sequential Circuits Based on Clock Gating Mechanisms,”

ED&TC’97: 1997 European Design and Test Conference,

Paris, France, March  1997, pp. 514–520.

43.  L. Benini, G. De Micheli, E. Macii, M. Poncino,

“Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs,”

IWLS’97: ACM/IEEE International Workshop on Logic Synthesis,

May 1997, Lake Tahoe, CA.

44.  L. Benini, G. De Micheli, E. Macii, M. Poncino, S. Quer, D. Sciuto, C. Silvano,

“On-Going Research on Address Bus Encoding for Low-Power: A Status Report,”

IWLS’97: ACM/IEEE International Workshop on Logic Synthesis,

May 1997, Lake Tahoe, CA.

45.  L. Benini, E. Macii, M. Poncino,

“Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control,”

DAC-34: 34th ACM/IEEE Design Automation Conference,

Anaheim, CA, June 1997, pp. 22–27

46.  L. Benini, G. De Micheli, E. Macii, M. Poncino, S. Quer,

“System-Level Power Optimization of Special Purpose Applications: The Beach Solution”,

ISLPED’97: ACM/IEEE International Symposium on Low Power Electronics and Design,

Monterey, CA, August 1997, pp. 24–29.

47.  G. Cabodi, P. Camurati, A. Lioy, M. Poncino, S. Quer,

“A Parallel Approach to Symbolic Traversal Based on Set Partitioning,”

IFIP CHARME’97: Correct Hardware Methodologies,

Montréal, Québec, Canada, October 1997, pp. 167–184.

48.  L. Benini, E. Macii, M. Poncino

“Efficient Controller Design for Telescopic Units,”

ISIS’97: IEEE International Conference on Innovative Systems in Silicon,

Austin, Texas, October 1997, pp 290–299.

49.  L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi,

“Fast Generation of Power Waveform for Hard Macros,”

ISIS’97: IEEE International Conference on Innovative Systems in Silicon,

Austin, Texas, October 1997, pp 331–337.

50.  L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi,

“Fast Power Estimation for Deterministic Input Streams,”

ICCAD’97: ACM/IEEE International Conference on CAD,

San Jose, CA, November 1997, pp. 494–497.

51.  L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi,

“Integrating Logic-level Power Management Techniques,”

SASIMI’97: Seventh Workshop on Synthesis And System Integration of Mixed Technologies,

Osaka, Japan, December 1997, pp. 59–65.

52.  F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto,

“Power Estimation of Behavioral VHDL Descriptions,”

DATE’98: IEEE Design Automation and Test in Europe,

Paris, France, February 1998, pp. 762–766.

53.  L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, M. Poncino,

“Timed Supersetting and the Synthesis of Large Telescopic Units,”

GLS-VLSI’98: IEEE Great Lakes Symposium on VLSI,

Lafayette, Lousiana, March 1998, pp. 331–337.

54.  L. Benini, A. Macii, E. Macii, M. Poncino

“Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding,”

GLS-VLSI’98: IEEE Great Lakes Symposium on VLSI,

Lafayette, Lousiana, March 1998, pp. 8–12.

55.  B. Kumthekar, E. Macii, M. Poncino, F. Somenzi,

“Simulation-Based Re-Synthesis of Sequential Circuits for Peak Sustainable Power Reduction,”

IWLS’98: ACM/IEEE International Workshop on Logic Synthesis,

Lake Tahoe, CA, June 1998, pp. 392–397.

56.  F. Ferrandi, A. Macii, E. Macii, M. Poncino, R. Scarsi, F. Somenzi

“Layout-Oriented Synthesis of PTL Circuits Based on BDDs,”

IWLS’98: ACM/IEEE International Workshop on Logic Synthesis,

Lake Tahoe, CA, June 1998, pp. 514–519.

57.  L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, M. Poncino

“Computational Kernels and their Application to Sequential Power Optimization,”

35th DAC: ACM/IEEE Design Automation Conference,

San Francisco, CA, 15–19 June 1998, pp. 764–769.

58.  A. Macii, E. Macii, M. Poncino, R. Scarsi,

“Stream Synthesis for Efficient Power Simulation Based on Spectral Transform,”

ISLPED’98: ACM/IEEE International Symposium on Low Power Electronics and Design,

Monterey, CA, August 1998, pp. 30–35.

59.  L. Benini, A. Macii, E. Macii, M. Poncino, R. Scarsi,

“A Stream Compaction Techniques Based on Multi-Level Power Simulation,”

PATMOS’98: Power and Timing Modeling, Optimization and Simulation,

Lingby, Denmark, October 1998, pp. 203–212.

60.  L. Benini, A. Macii, E. Macii, M. Poncino, R. Scarsi,

“F-Gate: A Device for Glitch Power Minimization,”

32nd Annual Asilomar Conference on Signals, Systems, and Computers,,

Pacific Grove, CA, November 1998, pp. 1047–1051.

61.  A. Macii, E. Macii, M. Poncino,

“Reducing Peak-Power Consumption of Combinational Test Sets,”

32nd Annual Asilomar Conference on Signals, Systems, and Computers,,

Pacific Grove, CA, November 1998, pp. 1042–1046.

62.  E. Macii, M. Poncino, R. Scarsi,

“A Comparative Study of Complexity-Based Capacitance Macromodels,

32nd Annual Asilomar Conference on Signals, Systems, and Computers,,

Pacific Grove, CA, November 1998, pp. 1038–1041.

63.  E. Macii, G. Odasso, M. Poncino,

“Comparing Different Boolean Unification Algorithms,”

32nd Annual Asilomar Conference on Signals, Systems, and Computers,,

Pacific Grove, CA, November 1998, pp. 1052–1056.

64.  F. Ferrandi, A. Macii, E. Macii, M. Poncino, R. Scarsi, F. Somenzi

“Symbolic Algorithms for Layout-Oriented PTL Synthesis,”

ICCAD’98: ACM/IEEE International Conference on CAD,

San Jose, CA, November 1998, pp. 235–241.

65.  C. Guardiani, A. Macii, E. Macii, M. Poncino, M. Rossello, R. Scarsi, C. Silvano, R. Zafalon,

“RTL Power Estimation in an Industrial Design Flow,”

IEEE Alessandro Volta Memorial International Workshop on Low Power Design,

Como, March 1999, pp. 91–96.

66.  R. Corgnati, E. Macii, M. Poncino

“Clustered Table-Based Macromodels for RTL Power Estimation”,

GLS-VLSI’99: IEEE Great Lakes Symposium on VLSI,

Ann Arbor, Michigan, March 1999, pp. 354-357.

67.  A. Macii,E. Macii, G. Odasso, M. Poncino, R. Scarsi,

“Regression-Based Macromodeling for Delay Estimation of Behavioral Components”,

GLS-VLSI’99: IEEE Great Lakes Symposium on VLSI,

Ann Arbor, Michigan, March 1999, pp. 188-191.

68.  L. Benini, A. Macii, E. Macii, M. Poncino, R. Scarsi

“Glitch Power Reduction by Gate Freezing,”

DATE’99: IEEE Design Automation and Test in Europe,

Munich, Germany, March 1999, pp. 137–141.

69.  L. Benini, A. Macii, E. Macii, M. Poncino, R. Scarsi

“Synthesis of Low-Overhead Interface Logic for Power Efficient Communication over Busses,”

36th ACM/IEEE Design Automation Conference, pp. 128–133,

New Orleans, LA, June 1999.

70.  L. Benini, A. Macii, G. Odasso, M. Poncino

“Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms,”

36th ACM/IEEE Design Automation Conference, pp. 247–252,

New Orleans, LA, June 1999.

71.  L. Benini, A. Macii, E. Macii, M. Poncino,

“Selective Instruction Compression for Memory Energy Reduction in Embedded Systems,”

ACM/IEEE International Symposium of Low Power Design and Electronics,

San Diego, CA, August 1999, pp. 206–211.

72.  A. Macii, E. Macii, M. Poncino, R. Scarsi,

“Extending Spectral Synthesis of Binary Streams to Sequential Circuits,”

IEEE Pacific Rim Conference on Communications, Computer and Signals,

Victoria, BC, Canada, August 1999, pp. 479–482.

73.  L. Benini, A. Macii, E. Macii, M. Poncino,

“Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems,”

Euromicro’99: 25th EuroMicro Conference,

Milano, September 1999, pp. 311-317.

74.  A. Bogliolo, E. Macii, V. Mihailovici, M. Poncino,

“Combinational Characterization-Based Power Macro-Models for Sequential Macros,”

PATMOS’99: Ninth International Workshop on Power and Timing Modeling, Optimization and Simulation,

Kos, Greece, October 1999, pp. 293–302.

75.  C. Anton, P. Civera, A. Bogliolo, I. Colonescu, E. Macii, M. Poncino,

“RTL Macromodels for non-Stationary Workloads,”

PATMOS’99: Ninth International Workshop Power and Timing Modeling, Optimization and Simulation,

Kos, Greece, October 1999, pp. 313–322.

76.  L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, R. Scarsi,

“Accurate Models for System-Level Battery Lifetime Estimation,”

PATMOS’99: Ninth International Workshop Power and Timing Modeling, Optimization and Simulation,

Kos, Greece, October 1999, pp. 345-354.

77.  A. Bogliolo, R. Corgnati, E. Macii, M. Poncino,

“Parameterized RTL Power Models for Combinational Soft Macros,”

ACM/IEEE International Conference on CAD,

San Jose, CA, November 1999, pp. 284–287.

78.  L. Benini, A. Bogliolo, E. Macii, M. Poncino, M. Surmei,

“Regression-Based RTL Power Models for Controllers”

GLS-VLSI’00: IEEE 10th Great Lakes Symposium on VLSI,

Evanston, IL, March 2000, pp. 147–152.

79.  L. Benini, M. Ferrero, A. Macii, E. Macii, M. Poncino,

“Supporting System-Level Power Exploration for Signal-Processing Applications”

GLS-VLSI’00: IEEE 10th Great Lakes Symposium on VLSI,

Evanston, IL, March 2000, pp. 17–22.

80.  M. Rossello, R. Zafalon, E. Macii, M. Poncino,

“Power Macromodeling for an High-Quality RT-level Power Estimator”,

ISQED’2000: 2000 International Symposium on Quality of Electronic Design,

San Jose, CA, March 2000, pp. 59–63.

81.  L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, R. Scarsi,

“An Event-Driven Battery Model for High-Level Power Estimation,”

in DATE 2000: IEEE Design and Test in Europe,

Paris, France, March 2000, pp. 35–39.

82.  L. Benini, A. Macii, E. Macii, M. Poncino,

“Analysis of Energy Dissipation in the Memory Hierarchy of Embedded Systems: A Case Study,”

MELECON’2000: IEEE Mediterranean Electrotechnical Conference,

Limassol, Cipro, May 2000, pp. 236-239.

83.  L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, R. Scarsi,

“Life-time Analysis of Batteries Used in Portable Digital Systems”

MELECON’2000: IEEE Mediterranean Electrotechnical Conference,

Limassol, Cyprus, May 2000, pp. 240–243.

84.  L. Benini, M. Ferrero, A. Macii, E. Macii, M. Poncino,

“Power/Performance Trade-Offs in the Implementation of Digital Filters: A Case Study,”

MELECON’2000: IEEE Mediterranean Electrotechnical Conference,

Limassol, Cyprus, May 2000, pp. 595-599.

85.  L. Benini, A. Macii, E. Macii, M. Poncino,

“Synthesis of Application-Specific Memories for Power Optimization in Embedded Systems,”

DAC-37: 37th Design Automation Conference,

Los Angeles, CA, June 2000, pp. 300-303.

86.  L. Benini, A. Macii, M. Poncino

“A Recursive Algorithm for Low-Power Memory Partitioning,”

ISLPED’00: ACM/IEEE International Symposium of Low Power Design and Electronics,

Rapallo, Italy, July 2000, pp. 78–83.

87.  C. Anton, A. Bogliolo, P. Civera, I. Colonescu, E. Macii, M. Poncino,

“RTL Estimation of Steering Logic Power,”

PATMOS’2000:International Workshop-Power And Timing Modeling, Optimiza tion and Simulation,

Hannover, Germany, September 2000, pp. 36–45.

88.  A. Bogliolo, E. Macii, V. Mihailovici, M. Poncino,

“Power Models for Semi-Autonomous RTL Macros”,

PATMOS’2000:International Workshop-Power And Timing Modeling, Optimiza tion and Simulation,

Hannover, Germany, September 2000, pp. 14–23.

89.  L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, R. Scarsi,

“Extending Lifetime of Portable Systems by Battery Scheduling,”

DATE’01: Design Automation and Test in Europe, Munich, Germany, March 2001, pp. 197–201.

90.  L. Benini, L. Macchiarulo, A. Macii, E. Macii, M. Poncino,

“From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip,”

DAC-38: 38th Design Automation Conference,

Las Vegas, NV, June 2001, pp. 784-789.

91.  L. Macchiarulo, E. Macii, M. Poncino,

“Low-Energy Encoding for Deep-Submicron Address Buses,”

ISLPED’01: ACM/IEEE International Symposium of Low Power Design and Electronics,

Huntington Beach, CA, August 2001, pp. 176–181.

92.  M. Anton, I. Colonescu, E. Macii, M. Poncino,

“Fast Characterization of RTL Power Macromodels”,

ICECS’01: 8th IEEE International Conference on Electronics, Circuits and Systems,

La Valletta, Malta, September 2001, pp. 1591–1594.

93.  L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino,

“Current-Controlled Policies for Battery-Driven Dynamic Power Management”,

ICECS’01: 8th IEEE International Conference on Electronics, Circuits and Systems,

La Valletta, Malta, September 2001, pp. 959-962.

94.  A. Bogliolo, I. Colonescu, R. Corgnati, E. Macii, M. Poncino,

"An RTL Power Estimation Tool with On-Line Model Building Capabilities",

PATMOS’2001: International Workshop-Power And Timing Modeling, Optimization and Simulation,

Yverdon-les-bains, Switzerland, September 2001.

95.  L. Macchiarulo, E. Macii M. Poncino,

“Wire Placement for Crosstalk Energy Minimization in Address Buses,”

DATE’02: Design Automation and Test in Europe,

Paris, France, March 2002, pp. 158–162.

96.  M. Donno, L. Macchiarulo, A. Macii, E. Macii M. Poncino,

“Enhanced Clustered Voltage Scaling for Low Power”,

GLS-VLSI’02: IEEE 12th Great Lakes Symposium on VLSI,

New York, NY, April 2002, pp. 18–23.

97.  N. Drago, F. Fummi, M. Poncino,

“Modeling network embedded systems with NS-2 and systemC”

ICCSC’02: 1st IEEE International Conference on Circuits and Systems for Communications,

St. Petersburg, Russia, June 2002, pp. 240–245.

98.  L. Benini, A. Macii, E. Macii, M. Poncino,

“Discharge current steering for battery lifetime optimization,”

ISLPED’02: ACM International Symposium on Low Power Electronics and Design,

Monterey, CA, August 2002, pp. 118–123.

99.  L. Benini, D. Bertozzi, D. Bruni, E. Dalla Mariga, N. Drago, F. Fummi, M. Poncino,

“ SystemC Co-Simulation of Multi-Processor Systems-on-Chip,”

ICCD’02: 20th IEEE International Conference on Computer Design,

Freiburg, Germany, September 2002, pp. 494–499.

100.  L. Benini, D. Bruni, N. Drago, F. Fummi, M. Poncino,

“Virtual In-Circuit Emulation for Timing Accurate System Prototyping”,

ASIC/SOC’02: 15th IEEE International ASIC/SOC Conference,

Rochester, NY, September 2002, pp. 49–53.

101.  A. Macii, E. Macii, M. Poncino,

“Improving the Efficiency of Memory Partitioning by Address Clustering,”

DATE’03: Design Automation and Test in Europe,

Munchen, Germany, March 2003, pp. 18–23.

102.  N. Drago, F. Fummi, M. Poncino, M. Monguzzi, G. Perbellini,

“Estimation of Bus Performance for a Tuplespace in an Embedded Architecture,”

DATE’03: Design Automation and Test in Europe,

Munchen, Germany, March 2003, pp. 188–193.

103.  L. Benini, A. Macii, E. Macii, E. Omerbegovic, M. Poncino, F. Pro,

“A Novel Architecture for Power Maskable Arithmetic Units,”

GLS-VLSI’03: IEEE 12th Great Lakes Symposium on VLSI,

Washington, DC, April 2003, pp. 136-140.

104.  E. Macii, M. Poncino, S. Salerno

“Combining Wire Swapping and Spacing for Low-Power Deep-Submicron Buses,”

GLS-VLSI’03: IEEE 12th Great Lakes Symposium on VLSI,

Washington, DC, April 2003, pp. 198–202.

105.  A. Macii, E. Macii, M. Poncino,

“Increasing the Locality of Memory Access Patterns by Low-Overhead Hardware Address Relocation,”

ISCAS’03: IEEE International Symposium on Circuits and Systems,

Bangkok, Thailand, May 2003, pp. 385–388.

106.  A. Fin, F. Fummi, M. Poncino, G. Pravadelli,

“A SystemC-based Framework for Properties Incompleteness Evaluation”,

MTV’03: IEEE International Workshop on Microprocessor Test and Verification

Austin, TX, May 2003.

107.  L. Benini, A. Macii, E. Macii, E. Omerbegovic, M. Poncino, F. Pro,

“Design of Power Maskable Unit for Cryptographic Applications,”

DAC-40: 40th Design Automation Conference,

Anaheim, CA, June 2003, pp. 36–41.

108.  F. Gallo, F. Fummi, S. Martini, G. Perbellini, M. Poncino, F. Ricciato,

“Synchronizing Network and Hardware Simulation,”

DAC-40: 40th Design Automation Conference,

Anaheim, CA, June 2003, pp. 42–47.

109.  L. Benini, A. Galati, A. Macii, E. Macii, M. Poncino

“Energy-Efficient Data Scrambling on Memory-Processor Interfaces,”

ISLPED’03: ACM International Symposium on Low Power Electronics and Design,

Seoul, Korea, August 2003, pp. 26–29.

110.  M. Bruno, A. Macii, M. Poncino “A Statistical Power Model for Non-Synthetic RTL Operators,”

PATMOS’03: 13th International Workshop on Power and Timing Modeling, Optimization and Simulation,

Torino, September 2003, pp. 208–218.

111.  “Heterogeneous Co-Simulation of Networked Embedded Systems,”

F. Fummi, S. Martini, G. Perbellini, M. Poncino, F. Ricciato, M. Turolla,

DATE’04: Design Automation and Test in Europe,

Paris, France, February 2004, pp .168-173.

112.  F. Fummi, S. Martini, M. Monguzzi, G. Perbellini, M. Poncino,

“Modeling and Analysis of Heterogeneous Industrial Networks Architectures,”

DATE’04: Design Automation and Test in Europe,

Feb. 16-20, 2004, Paris, France, February 2004, pp. 342-343.

113.  F. Fummi, S. Martini, G. Perbellini, M. Poncino,

“Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC,”

DATE’04: Design Automation and Test in Europe,

Paris, France, February 2004, pp. 564-569.

114.  K. Patel, E. Macii, M. Poncino,

“Synthesis of Partitioned Shared Memory Architectures for Energy-efficient Multi-Processor SoC,”

DATE’04: Design Automation and Test in Europe,

Paris, France, February 2004, pp. 700-701.

115.  A. Bocca, S. Salerno, E. Macii, M. Poncino,

“Energy-Efficient Bus Encoding for LCD Displays,”

GLS-VLSI’04: IEEE 13th Great Lakes Symposium on VLSI,

Boston, MA, April 2004.

116.  M. Loghi, L. Benini, M. Poncino,

“Cycle-Accurate Power Analysis for Multiprocessor Systems-on-a-Chip,”

GLS-VLSI’04: IEEE 13th Great Lakes Symposium on VLSI,

Boston, MA, April 2004.

117.  K. Patel, E. Macii, M. Poncino,

“Energy-Performance Tradeoffs for the Shared Memory in Multi-Processor Systems-on-Chip,”

ISCAS’04: IEEE International Symposium on Circuits and Systems,

Vancouver, Canada, May 2004, pp. 361–364.

118.  S. Salerno, E. Macii, M. Poncino,

“Crosstalk Energy Reduction by Temporal Shielding,”

ISCAS’04: IEEE International Symposium on Circuits and Systems,

Vancouver, Canada, May 2004, pp. 749–752.

119.  A. Bocca, S. Salerno, E. Macii, M. Poncino,

“Limited Intra-Word Transition Codes: An Energy-Efficient Bus Encoding for LCD Display Interfaces,”

ISPLED’04: ACM/IEEE International Symposium on Low-Power Electronics and Design,

Newport Beach, CA, August 2004, pp. 206–211.

120.  S. Salerno, E. Macii, M. Poncino,

“A Low-Power Encoding Scheme for GigaByte Video Interfaces,”

PATMOS 2004: 14th International Workshop on Power and Timing Modeling, Optimization and Simulation,

Santorini, Greece, September 2004, pp. 58–68.

121.  M. Loghi, L. Benini, M. Poncino,

“Empirical Macromodeling of Operating System Communication Primitives,”

PARTES’04: International Workshop on Probabilistic Analysis Techniques for Real-Time and Embedded Systems,

Pisa, September 2004.

122.  M. Loghi, L. Benini, M. Poncino,

“Analyzing Power Consumption of Message Passing Primitives in a Single-chip Multiprocessor”,

ICCD’04: International Conference on Computer Design,

San Jose (CA), October 2004, pp. 393-396

123.  F. Fummi, S. Martini, M. Monguzzi, G. Perbellini, M. Poncino,

“Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures”,

ICCD’04: International Conference on Computer Design,

San Jose (CA), October 2004, pp. 496-501

124.  P. Kimish, L. Benini, E. Macii, M. Poncino,

“Reducing Cache Misses by Application-Specific Re-Configurable Indexing,”

ICCAD’04: ACM/IEEE International Conference on CAD,

San Jose (CA), November 2004, pp. 56–59.

125.  M. Loghi, M. Poncino,

“Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs:

Snoop-Based Cache Coherence vs. Software Solutions,”

DATE’05: Design, Automation and Test in Europe,

Munich, Germany, March 2005, pp. 508–513.

126.  F. Fummi, M. Loghi, S. Martini, M. Monguzzi, G. Perbellini, M. Poncino,

“Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation,”

DATE’05: Design, Automation and Test in Europe,

Munich, Germany, March 2005 pp. 798 - 803.

127.  M. Loghi, P. Azzoni, M. Poncino,

“Tag Overflow Buffering: An Energy-Efficient Cache Architecture,”

DATE’05: Design, Automation and Test in Europe,

Munich, Germany, March 2005 pp. 520 - 525.

128.  K. Patel, E. Macii, M. Poncino,

“Zero Clustering: an Approach to Extend Zero Compression to Instruction Caches,”

GLS-VLSI’05: IEEE 14th Great Lakes Symposium on VLSI,

Chicago, IL, April 2005, pp.56 - 59.

129.  M. Loghi, M. Letis, L. Benini, M. Poncino,

“Exploring the Energy Efficiency of Cache Coherence Protocols in Single-Chip Multi-Processors,”

GLS-VLSI’05: IEEE 14th Great Lakes Symposium on VLSI,

Chicago, IL, April 2004, pp. 276 - 281.

130.  A. Chakraborty, E. Macii, D. Pandini, M. Poncino, A. Macii

“Evaluating Regularity Extraction in Logic Synthesis,”

ISSCS’05: IEEE Intenational Symposium on Signals, Circuits and Systems,

Iasi, Romania, July 2005.

131.  “Energy-Efficient Encoding for Secure Digital LCD Interfaces,” A. Chakraborty, E. Macii, M. Poncino,

ISSCS’05: IEEE Intenational Symposium on Signals, Circuits and Systems,

Iasi, Romania, July 2005.

132. A. Chakraborty, E. Macii, M. Poncino,

“Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding,”

PATMOS 2005: 15th International Workshop on Power and Timing Modeling, Optimization and Simulation,

Leuven, Belgium, September 2005, pp. 297-307.

       133. K. Patel, E. Macii, M. Poncino,

“Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs,”

PATMOS 2005: 15th International Workshop on Power and Timing Modeling, Optimization and Simulation,

Leuven, Belgium, September 2005, pp. 466-476.

134. A. Nurrachmat, S. Salerno, E. Macii, M. Poncino,

“Energy-Efficient Color Approximation for Digital LCD Interfaces,”

ICCD’05: International Conference on Computer Design,

San Jose (CA), October 2005, pp. 81–86.

135. K. Patel, E. Macii, M. Poncino,

“Frame Buffer Energy Optimization by Pixel Prediction,”

ICCD’05: International Conference on Computer Design,

San Jose (CA), October 2005, pp. 98–101.

136. A. Chakraborty, P. Sithambaram, K. Duraisami, A. Macii, E. Macii, M. Poncino,

“Thermal resilient bounded-skew clock tree optimization methodology”,

DATE’06: IEEE Design Automation and Test in Europe,

Munich, Germany, March 2006, pp. 832–837.

137. F. Fummi, G. Perbellini, M. Loghi, M. Poncino,

“ISS-Centric Modular HW/SW Co-Simulation,”

GLS-VLSI’06: IEEE 16th Great Lakes Symposium on VLSI,

Philadelphia, PA, April 2006, pp. 31–36.

138. K. Patel, L. Benini, E. Macii, M. Poncino,

“STV-Cache: a Leakage Energy-Efficient Architecture for Data Caches,”

GLS-VLSI’06: IEEE 16th Great Lakes Symposium on VLSI, Philadelphia, PA, April 2006, pp. 404–409,

        139. A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, M. Poncino

“Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective,”

PATMOS 2006: 16th International Workshop on Power and Timing Modeling, Optimization and Simulation,

Montpellier, France, September 2005, pp. 214-224.

140. A. Nurrachmat, E. Macii, M. Poncino,

“Low-Energy Pixel Approximation for DVI-Based LCD Interfaces”,

ISCAS-06: IEEE International Conference on Circuits and Systems, Kos Island, Greece, May 2006, pp. 4337-4440.

141. A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, M. Poncino,

“Implications of Ultra Low-Voltage Devices on Design Techniques for Controlling Leakage in NanoCMOS Circuits”,

ISCAS-06: IEEE International Conference on Circuits and Systems, Kos Island, Greece, May 2006, pp. 33-36.

142. A. Chakraborty, A. Sathanur, P. Sithambaram, K. Duraisami, L. Benini, A. Macii, E. Macii, M. Poncino,

“Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers,”

ISLPED’06: ACM International Symposium on Low Power Electronics and Design,

Tegernsee, Germany, October 2006, pp. 162--167.

143. M. Loghi, M. Poncino, L. Benini

“Synchronization-Driven Dynamic Speed Scaling for MPSoCs,”

ISLPED’06: ACM International Symposium on Low Power Electronics and Design,

Tegernsee, Germany, October 2006, pp. 346--349.

144. A. Sathanur, A. Calimera, A. Macii, E. Macii, M. Poncino, L. Benini,

“Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing,”

DATE’07: IEEE Design Automation and Test in Europe,

Nice, France, April 2006, pp. 1-6.

145. O. Golubeva, M. Loghi, M. Poncino, E. Macii,

“Architectural Leakage-Aware Management of Partitioned Scratchpad Memories,”

DATE’07: IEEE Design Automation and Test in Europe,

Nice, France, April 2007, pp. 1665-1670.

146. A. Calimera, A. Pullini, A. Macii, E. Macii, M. Poncino

“Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology”

GLS-VLSI’07: IEEE 16th Great Lakes Symposium on VLSI,

Stresa, Italy, March 2007, pp. 501--504.

147. O. Golubeva, M. Loghi, M. Poncino

“On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors”

GLS-VLSI’07: IEEE 16th Great Lakes Symposium on VLSI,

Stresa, Italy, March 2007, pp. 489—492.

148. K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, M. Poncino,

“Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew,”

ISCAS-07: IEEE International Conference on Circuits and Systems,

New Orleans, LA, May 2007, pp. 1061-1064.

149. O. Golubeva, M. Loghi, M. Poncino, E. Macii,

“Locality Driven Architectural Cache Subbanking for Leakage Energy Reduction,”

ISLPED’07: ACM International Symposium on Low Power Electronics and Design,

Portland, OR, August 2007, pp. 104—109.

150. A. Sathanur, A. Pullini, A. Macii, E. Macii, M. Poncino

“Timing Driven Row-Based Power Gating,”

ISLPED’07: ACM International Symposium on Low Power Electronics and Design,

Portland, OR, August 2007, pp.274--279.

151.  Sathanur, A. Pullini, L. Benini, A. Macii, E. Macii, M. Poncino,
“A Scalable Algorithmic Framework for Row-Based Power-Gating”
DATE '08: Design, Automation and Test in Europe, 2008.
Munich, Germany 10-14 March 2008, pp. 379 – 384.

152.  L. Benini, A. Macii, E. Macii, M. Poncino, A. Sathanur,
“Optimal sleep transistor synthesis under timing and area constraints”,
GLS­VLSI­08: ACM/IEEE 18th Great Lakes Symposium on VLSI, Orlando, Florida, May 2008,, USA, pp. 177­182.

153.  A. Calimera, I. Bahar, E. Macii, M. Poncino,
Temperature-Insensitive Synthesis Using Multi-Vt Libraries”
GLS­VLSI­08: ACM/IEEE 18th Great Lakes Symposium on VLSI, Orlando, Florida, May 2008,, USA, pp.5-10.

154.  K. Duraisami, E. Macii, M. Poncino
“Energy efficiency bounds of pulse-encoded buses”
GLSVLSI '08: ACM/IEEE 18th Great Lakes symposium on VLSI, Orlando, FL, May 2008, pp. 183-188.

155.  A. Sathanur, A. Calimera, A. Pullini, L. Benini, A. Macii, E. Macii, M. Poncino,
“On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits”
ISCAS’08: IEEE International Symposium on Circuits and Systems, 2008.
Seattle, WA, 18-21 May 2008 pp. 2761 – 2764.

156.  A. Calimera, R. I. Bahar, E. Macii, M. Poncino
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits”
ISLPED '08: International Symposium on Low power Electronics and Design,
Bangalore, India, August 2008, pp. 217-220.

157.  A.  Sathanur, L. Benini, A, Macii, E. Macii, M. Poncino
“Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction”
ISLPED '08: International Symposium on Low power Electronics and Design,
Bangalore, India, August 2008, pp. 51-56.

158.  A. Sathanur, L. Benini, A. Macii, E. Macii, M. Poncino,
 “Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating”
PATMOS’08: Power and Timing Modeling, Optimization and Simulation,
Lisbon, Portugal, September 2008, pp. 203–212.

159.  A. Calimera, R. I. Bahar, E. Macii, M. Poncino,
“Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis”
THERMINIC 2008. 14th International Workshop on Thermal Investigation of ICs and Systems,
Rome, Italy, 24-26 Sept. 2008, pp. 31 – 36.

160.  L. Bolzani, A. Calimera, A. Macii, E. Macii, M. Poncino,
“Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits”, 
DSD­08: IEEE 11th Euromicro Conference on Digital System Design,
Parma, Italy, September 2008, pp. 298­303.

 

161.  K. Duraisami, E. Macii, M. Poncino,
“Using Soft-Edge Flip-Flops to Compensate NBTI-induced Delay Degradation”
GLSVLSI '09: ACM/IEEE 18th Great Lakes symposium on VLSI,
Boston, Ma, May 2009, pp. 169-172.

162.  A. Calimera, E. Macii, M. Poncino
“NBTI-Aware Sleep Transistor Design for Reliable Power-Gating”,
GLSVLSI '09: ACM/IEEE 18th Great Lakes symposium on VLSI,
Boston, Ma, May 2009, pp. 333-338.

163.  C. Ferri, R. Bahar, M. Loghi, M. Poncino
“Energy-Optimal Synchronization Primitives for Single-Chip Multi-Processors”,
GLSVLSI '09: ACM/IEEE 18th Great Lakes symposium on VLSI, Boston, Ma,
May 2009, pp
141-144.

164.  L . Bolzani. A. Calimera, A. Macii, E. Macii, M. Poncino
“Enabling Concurrent Clock and Power Gating in an Industrial Design Flow”,
DATE '09: Design, Automation and Test in Europe, 2009.
Nice, France, April 2009, pp.
334-339.

165.  L . Bolzani. A. Calimera, A. Macii, E. Macii, M. Poncino ,
“Placement-Aware Clustering for Integrated Clock and Power Gating”,
ISCAS’09: IEEE International Symposium on Circuits and Systems, 2009,
Taipei, Taiwan , May 2009, pp.
1723-1726.

166.  A. Calimera, E. Macii, M. Poncino
“NBTI-Aware
power gating for concurrent leakage and aging optimization”,
ISLPED '09: International Symposium on Low power Electronics and Design,
San Francisco, CA, August 2009, pp. 127-132.

167.  W. Liu, A. Calimera, A. Nannarelli, E Macii, M Poncino.
”On-chip Thermal Modeling Based on SPICE Simulation”
PATMOS’09: Power and Timing Modeling, Optimization and Simulation,
Delft, The Netherland, September 2009, pp. 66-75.

168.  A. Bonanno, A. Bocca, A. Macii, E. Macii, M. Poncino,
“Data-Driven Clock Gating for Digital Filters”,
PATMOS’09: Power and Timing Modeling, Optimization and Simulation,
Delft, The Netherland, September 2009, pp. 96-105.

169.  G. Upasani, A. Calimera, A. Macii, E. Macii, M. Poncino.
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering “,
PATMOS’09: Power and Timing Modeling, Optimization and Simulation,
Delft, The Netherland, September 2009, pp. 227-236.

 

170.  W. Liu, A. Calimera, A. Nannarelli, E Macii, M Poncino.
”Post-placement temperature reduction techniques”,

         DATE‘10: Design, Automation and Test in Europe, 2010.
        
Dresden, Germany, March 2010, pp. 634-637.

171.  A. Calimera, E. Macii, M. Poncino
”Analysis of NBTI-Induced SNM Degradation in Power-Gated SRAM Cells”
ISCAS’10: IEEE International Symposium on Circuits and Systems, 2010,
Paris, France, May 2010, pp. 785-788.
           

172.  A. Calimera, M. Loghi, E. Macii, M. Poncino
”Aging Effects of Leakage Optimizations for Caches”
GLSVLSI '10: ACM/IEEE 20th Great Lakes symposium on VLSI,
Providence, RI, May 2010, pp. 95—98.

173.  D. Cuesta, J. Ayala, J. Hidalgo, M.Poncino, A. Acquaviva, E.Macii
”Thermal-Aware Floorplanning Exploration for 3D Multi-Core Architectures”
GLSVLSI '10: ACM/IEEE 20th Great Lakes symposium on VLSI,
Providence, RI, May 2010, pp 99—102.
        

174.  A. Acquaviva, A. Calimera, A. Macii, E. Macii, M. Poncino, M. Giaconia, C. Parrella,
”An Integrated Thermal Estimation Framework for Industrial Embedded Platforms”
GLSVLSI '10: ACM/IEEE 20th Great Lakes symposium on VLSI,  
Providence, RI, May 2010,  pp. 293—298.

175.  A. Calimera,  E. Macii, M. Poncino,
“Power-Gating: More Than Leakage Savings”,
PRIME’2010: 6th Conference on Ph.D. Research in Microelectronics & Electronics, 
Berlin, Germany, July 2010, pp. 1-4.

176.  A. Calimera, M. Loghi,  E. Macii, M. Poncino,
Dynamic indexing: Concurrent leakage and aging optimization for caches”,
ISLPED '10: International Symposium on Low power Electronics and Design,
Austin, TX, August 2010, pp. 343-348.

177.  A. Calimera, A. Macii, E. Macii, M. Poncino, S. Rinaudo
 “THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future’’,
THERMINIC’10: 16th International Workshop on Thermal investigations of ICs and Systems, 
Barcelona,  Spain, October 2010, pp. 171—176.

178.  “Minimizing temperature sensitivity of dual-Vt CMOS circuits using simulated-annealing on ISING-like models”,
M. Caldera, A. Calimera, A. Macii, E. Macii, M. Poncino,
THERMINIC’10: 16th International Workshop on Thermal investigations of ICs and Systems, 
Barcelona, Spain, October 2010, pp. 189—194.

179.  M. Caldera, A. Calimera, A. Macii, E. Macii, M. Poncino,
“Minimizing Temperature Sensitivity of Dual-Vt CMOS Circuits Using Simulated-Annealing on ISING-like Models”,
IEEE THERMINIC-10: IEEE 16th International Workshop on Thermal Investigation of ICs and Systems, December 2010.

180.  A. Calimera, A. Macii, E. Macii, S. Rinaudo, M. Poncino,
” THERMINATOR: Modeling, Control and Management of Thermal Effects in Electronic Circuits of the Future”,
IEEE THERMINIC-10: IEEE 16th International Workshop on Thermal Investigation of ICs and Systems, December 2010.

 

181.  S. Rinaudo, G. Gangemi, A. Calimera, A. Macii, M. Poncino,
“Moving to Green: from Stand-Alone Power-Aware IC Designs to Energy Efficient Design Solutions for Heterogeneous Electronics Systems,”
DATE‘11: Design, Automation and Test in Europe, Grenoble, France, March 2011.

182.  M. Ottella, M. Sciolla, A. Acquaviva, M. Poncino,
“System Level Techniques to Improve Reliability in High Power Microcontrollers for Automotive Applications”
DATE‘11: Design, Automation and Test in Europe, Grenoble, France, March 2011.

183.  A. Calimera, M. Loghi, E. Macii, M. Poncino
“Partitioned Cache Architectures for Reduced NBTI-Induced Aging”,
DATE‘11: Design, Automation and Test in Europe, Grenoble, France, March 2011, pp.
938-943.

184.  A. Calimera, M. Loghi, E. Macii, M. Poncino
“Frequent Accesses Buffering for Reduced Cache Aging”,
GLSVLSI '11: ACM/IEEE 21st Great Lakes symposium on VLSI,  Lausanne, Switzerland, May 2010, pp. 295-300.

185.  A. Calimera, A. Macii, E. Macii, M. Poncino,
 “Enabling Energy Efficient and Variation Tolerant Nanoelectronics Design for Healthcare and Medical Applications”,
EUNANO 2011.

186.  H.  Karimiyan, A. Calimera, A. Macii, E. Macii and M. Poncino
 “An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs”,
PATMOS’11: Power and Timing Modeling, Optimization and Simulation, Madrid, Spain, Volume 6951/2011, pp. 162-172.

187.  K. Lingasubramanian, A. Calimera, A. Macii, E. Macii and M. Poncino,
“Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating”
PATMOS’11: Power and Timing Modeling, Optimization and Simulation, Madrid, Spain, Volume 6951/2011, pp. 214-225.

188.  Y. Kim, S. Park, Y. Wang, Q. Xie, N. Chang, M. Poncino and M. Pedram,
“Balanced Reconfiguration of Storage Banks in a Hybrid Electrical Energy Storage System”,
ICCAD 2011: ACM/IEEE International Conference on CAD, San Jose, CA, November 2011.

 

189.   S. Miryala, A. Calimera, E. Macii, M. Poncino,
“IR-Drop Analysis of Graphene-Based Power Distribution Networks”,
DATE‘12: Design, Automation and Test in Europe, Dresden, Germany, March 2012, to appear.

190.  H. Mahmood, M. Loghi, E. Macii, M. Poncino,
“Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization”.
DATE‘12: Design, Automation and Test in Europe, Dresden, Germany, March 2012, to appear.

191.  Y. Wang. Q. Xie, Y. Kim, N. Chang, M. Poncino, M. Pedram,
Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems”,
DATE‘12: Design, Automation and Test in Europe, Dresden, Germany, March 2012, to appear.

192.  H. Mahmood, M. Loghi, E. Macii, M. Poncino,
“Aging-Aware Caches with Graceful Degradation of Performance”,
submitted to ISCAS’2012.