1st Reliable Field
Programmable Logic


The 1st Reliable Field Programmable Logic (RPFL) workshop 2017 RFPL provides a forum for researchers active in domains within the reliable programmable logic.

Its main focus is on Field Programmable Gate Array devices, tools and algorithm for reconfigurability, versatility, high speed in highly reliable environments.

The main objective of this is to exchange information related to new techniques that enhance the in-circuit debuggin capabilities, or enhance the reliability of FPGAs versus radiation particles.

This workshop can be of interest for verification and debugging experts that wish to exchange information and share results about new techniques on mitigation and in-circuit debug.


Papers are limited to 2 pages and should be submitted in single-spaced, double column, 10 point type on a 8.5″ X 11″ or equivalent paper with 1″ margins on all sides. Each submission should contain: a title, the authors’ names and affiliations, a maximum 150 words abstract, the body of the paper, and references based on the IEEE template.

September 7, 2017

Ghent, Belgium